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eroflex circuit technology - advanced multichip modules ? scd1667 rev a 4/28/98 general description the act?f128k32 is a high speed, 4 megabit cmos flash multichip module (mcm) designed for full temperature range military, space, or high reliability applications. the mcm can be organized as a 128k x 32 bits, 256k x 16 bits or 512k x 8 bits device and is input ttl and output cmos compatible. the command register is written by bringing we to a logic low level (v i l ), while ce is low and oe is at logic high level (v i h ) . reading is accomplished by chip enable ( ce ) and output enable ( oe ) being logically active, see figure9. access time grades of 60ns, 70ns, 90ns, 120ns and 150ns maximum are standard. the act?f128k32 is packaged in a hermetically features n 4 low power 128k x 8 flash die in one mcm package n organized as 128k x 32 l user configurable to 256k x 16 or 512k x 8 l upgradable to 512k x 32 in same package style n access times of 60, 70, 90, 120 and 150ns n +5v programing, 5v 10% supply n 100,000 erase/program cycles typical, 0c to +70c n low standby current n ttl compatible inputs and cmos outputs n embedded erase and program algorithms n page program operation and internal program control time n commercial, industrial and military temperature ranges n mil-prf-38534 compliant mcms available n industry standard pinouts n packaging ? hermetic ceramic l 68 lead, .88" x .88" x .160" single-cavity small outline gull wing, aeroflex code# "f5" (drops into the 68 lead jedec .99"sq cqfj footprint) l 66 pin, 1.08" x 1.08" x .160" pga type, no shoulder, aeroflex code# "p3" l 66 pin, 1.08" x 1.08" x .185" pga type, with shoulder, aeroflex code# "p7" n sector architecture (each die) l 8 equal size sectors of 64k bytes each l any combination of sectors can be erased with one command sequence l supports full chip erase n desc smd# 5962?94716 released (p3,p7,f5) 128kx8 128kx8 128kx8 128kx8 ce 4 oe a 0 ?a 16 i/o 0-7 i/o 8-15 i/o 16-23 i/o 24-31 8 8 8 8 ce 3 we 4 we 3 we 2 we 1 ce 1 ce 2 block diagram ? pga type package(p3,p7) & cqfp(f5) pin description i/o 0-31 data i/o a 0?16 address inputs we 1-4 write enables ce 1-4 chip enables oe output enable v cc power supply gnd ground nc not connected circuit technology www.aeroflex.com act?f128k32 high speed 4 megabit flash multichip module
aeroflex circuit technology scd1667 rev a 4/28/97 plainview ny (516) 694-6700 2 sealed co-fired ceramic 66 pin, 1.08"sq pga or a 68 lead, .88" sq ceramic gull wing cqfp package for operation over the temperature range of -55c to +125c and military environment. each flash memory die is organized as 128kx8 bits and is designed to be programmed in-system with the standard system 5.0v vcc supply. a 12.0v v p p is not required for write or erase operations. the mcm can also be reprogrammed with standard eprom programmers (with the proper socket). the standard act-f128k32 offers access times between 60ns and 150ns, allowing operation of high-speed microprocessors without wait states. to eliminate bus contention, the device has separate chip enable ( ce ) and write enable ( we ). the act-f128k32 is command set compatible with jedec standard 1 mbit eeproms. commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state-machine which controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from 12.0v flash or eprom devices. the act-f128k32 is programmed by executing the program command sequence. this will invoke the embedded program algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. typically, each sector can be programmed and verified in less than 0.3 second. erase is accomplished by executing the erase command sequence. this will invoke the embedded erase algorithm which is an internal algorithm that automatically preprograms the array, (if it is not already programmed before) executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper cell margin. each die in the module or any individual sector of the die is typically erased and verified in 1.3 seconds (if already completely preprogrammed). each die also features a sector erase architecture. the sector mode allows for 16k byte blocks of memory to be erased and reprogrammed without affecting other blocks. the act-f128k32 is erased when shipped from the factory. the device features single 5.0v power supply operation for both read and write functions. lnternally generated and regulated voltages are provided for the program and erase operations. a low v c c detector automatically inhibits write operations on the loss of power. the end of program or erase is detected by data polling of d 7 or by the toggle bit feature on d 6 . once the end of a program or erase cycle has been completed,-+ the device internally resets to the read mode. all bits of each die, or all bits within a sector of a die, are erased via fowler-nordhiem tunneling. bytes are programmed one byte at a time by hot electron injection. desc standard military drawing (smd) numbers are released. general description, cont?d ,
aeroflex circuit technology scd1667 rev a 4/28/97 plainview ny (516) 694-6700 3 z absolute maximum ratings parameter symbol range units case operating temperature t c -55 to +125 c storage temperature range t s t g -65 to +150 c supply voltage range v c c -2.0 to +7.0 v signal voltage range (any pin except a 9 ) note 1 v g -2.0 to +7.0 v maximum lead temperature (10 seconds) 300 c data retention 10 years endurance (write/erase cycles) 100,000 minimum a 9 voltage for sector protect, note 2 v i d -2.0 to +14.0 v note 1. minimum dc voltage on input or i/o pins is -0.5v. during voltage transitions, inputs may undershoot v s s to -2.0v for periods of up to 20ns. maximum dc voltage on input and i/o pins is v c c + 0.5v. during voltage transitions, inputs and i/o pins may overshoot to v c c + 2.0v for periods up to 20 ns. note 2. minimum dc input voltage on a 9 is -0.5v. during voltage transitions, a9 may undershoot v s s to -2.0v for periods of up to 20ns. maximum dc input voltage on a 9 is +12.5v which may overshoot to 14.0v for periods up to 20ns. normal operating conditions symbol parameter minimum maximum units v c c power supply voltage +4.5 +5.5 v v i h input high voltage +2.0 v cc + 0.5 v v i l input low voltage -0.5 +0.8 v t c operating temperature (military) -55 +125 c v i d a 9 voltage for sector protect 11.5 12.5 v capacitance (v i n = 0v, f = 1mhz, t c = 25c) symbol parameter maximum units c a d a 0 ? a 16 capacitance 50 pf c o e oe capacitance 50 pf c w e write enable capacitance cqfp(f5) package 20 pf pga(p3,p7) package 20 pf c c e chip enable capacitance 20 pf c i / o i/o 0 ? i/o 31 capacitance 20 pf parameters guaranteed but not tested dc characteristics ? cmos compatible (vcc = 5.0v, vss = 0v, t c = -55c to +125c, unless otherwise indicated) parameter sym conditions speeds 60, 70, 90, 120 & 150ns minimum maximum units input leakage current i l i v c c = 5.5v, vi n = gnd to v c c 10 a output leakage current i l o x 32 v c c = 5.5v, vi n = gnd to v c c 10 a active operating supply current for read (1) i c c 1 ce = v i l , oe = v i h , f = 5mhz 140 ma active operating supply current for program or erase(2) i c c 2 ce = v i l , oe = v i h 200 ma standby supply current i c c 3 v c c = 5.5v, c e = v i h , f = 5mhz 6.5 ma static supply current (4) i c c 4 v c c = 5.5v, ce = v i h 0.6 ma output low voltage v o l i o l = +8.0 ma, v c c = 4.5v 0.45 v output high voltage v o h 1 i o h = ?2.5 ma, v c c = 4.5v 0.85 x v c c v output high voltage (4) v o h 2 i o h = ?100 a, v c c = 4.5v v c c ? 0.4 v low power supply lock-out voltage (4) v l k o 3.2 v note 1. the icc current listed includes both the dc operating current and the frequency dependent component (at 5 mhz). the freq uency component typically is less than 2 ma/mhz, with oe at v i n . note 2. icc active while embedded algorithm (program or erase) is in progress. note 3. dc test conditions: v i l = 0.3v, v i h = v c c - 0.3v, unless otherwise indicated note 4. parameter guaranteed but not tested.
aeroflex circuit technology scd1667 rev a 4/28/97 plainview ny (516) 694-6700 4 characteristics ? read only operations (vcc = 5.0v, vss = 0v, t c = -55c to +125c) parameter symbol jedec stand?d ?60 min max ?70 min max ?90 min max ?120 min max ?150 min max units read cycle time t a v a v t r c 60 70 90 120 150 ns address access time t a v q v t a c c 60 70 90 120 150 ns chip enable access time t e l q v t c e 60 70 90 120 150 ns output enable to output valid t g l q v t o e 30 35 40 50 55 ns chip enable to output high z (1) t e h q z t d f 20 20 25 30 35 ns output enable high to output high z (1) t g h q z t d f 20 20 25 30 35 ns output hold from address, ce or oe change, whichever is first t a x q x t o h 0 0 0 0 0 ns note 1. guaranteed by design, but not tested ac characteristics ? write/erase/program operations, we controlled (vcc = 5.0v, vss = 0v, tc = -55c to +125c) parameter symbol jedec stand?d ?60 min max ?70 min max ?90 min max ?120 min max ?150 min max units write cycle time t a v a c t w c 60 70 90 120 150 ns chip enable setup time t e l w l t c e 0 0 0 0 0 ns write enable pulse width t w l w h t w p 30 35 45 50 50 ns address setup time t a v w l t a s 0 0 0 0 0 ns data setup time t d v w h t d s 30 30 45 50 50 ns data hold time t w h d x t d h 0 0 0 0 0 ns address hold time t w l a x t a h 45 45 45 50 50 ns chip enable hold time (1) t w h e h t c h 0 0 0 0 0 ns write enable pulse width high t w h w l t w p h 20 20 20 20 20 ns duration of byte programming operation t w h w h 1 14 typ 14 typ 14 typ 14 typ 14 typ s sector erase time t w h w h 2 60 60 60 60 60 sec chip erase time t w h w h 3 120 120 120 120 120 sec read recovery time before write (1) t g h w l 0 0 0 0 0 s vcc setup time (1) t v c e 50 50 50 50 50 s chip programming time 12.5 12.5 12.5 12.5 12.5 sec output enable setup time (1) t o e s 0 0 0 0 0 ns output enable hold time (1) t o e h 10 10 10 10 10 ns note 1. guaranteed by design, but not tested ac characteristics ? write/erase/program operations, ce controlled (vcc = 5.0v, vss = 0v, t c = -55c to +125c) parameter symbol jedec stand?d ?60 min max ?70 min max ?90 min max ?120 min max ?150 min max units write cycle time t a v a c t w c 60 70 90 120 150 ns write enable setup time t w l e l t w s 0 0 0 0 0 ns chip enable pulse width t e l e h t c p 35 35 45 50 55 ns address setup time t a v e l t a s 0 0 0 0 0 ns data setup time t d v e h t d s 30 30 45 50 55 ns data hold time t e h d x t d h 0 0 0 0 0 ns address hold time t e l a x t a h 45 45 45 50 55 ns write enable hold time (1) t e h w h t w h 0 0 0 0 0 ns write select pulse width high t e h e l t c p h 20 20 20 20 20 ns duration of byte programming t w h w h 1 14 typ 14 typ 14 typ 14 typ 14 typ s sector erase time t w h w h 2 60 60 60 60 60 sec chip erase time t w h w h 3 120 120 120 120 120 sec read recovery time (1) t g h e l 0 0 0 0 0 ns chip programming time 12.5 12.5 12.5 12.5 12.5 sec note 1. guaranteed by design, but not tested
aeroflex circuit technology scd1667 rev a 4/28/97 plainview ny (516) 694-6700 5 device operation the act-f128k32 mcm is composed of four, one megabit flash eeproms. the following description is for the individual flash eeprom device, is applicable to each of the four memory chips inside the mcm. chip 1 is distinguished by ce 1 and i/o 1-7 , chip 2 by ce 2 and i/0 8-15 , chip 3 by ce 3 and i/0 16-23 , and chip 4 by ce 4 and i/0 24-31 . programming of the act-f128k32 is accomplished by executing the program command sequence. the program algorithm, which is an internal algorithm, automatically times the program pulse widths and verifies proper cell status. sectors can be programed and verified in less than 0.3 second. erase is accomplished by executing the erase command sequence. the erase algorithm, which is internal, automatically preprograms the array if it is not already programed before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper cell status. the entire memory is typically erased and verified in 3 seconds (ifpre-programmed). the sector mode allows for 16k byte blocks of memory to be erased and reprogrammed without affecting other blocks. bus operation read the act-f128k32 has two control functions, both of which must be logically active, to obtain data at the outputs. chip enable ( ce ) is the power control and should be used for device selection. output-enable ( oe ) is the output control and should be used to gate data to the output pins of the chip selected. figure 7 illustrates ac read timing waveforms. output disable with output-enable at a logic high level (v i h ), output from the device is disabled. output pins are placed in a high impedance state. standby mode the act-f128k32 has two standby modes, a cmos standby mode ( ce input held at vcc + 0.5v), where the current consumed is typically less than 400 a; and a ttl standby mode ( ce is held v i h ) is approximately 1 ma. in the standby mode the outputs are in a high impedance state, independent of the oe input. if the device is deselected during erasure or programming, the device will draw active current until the operation is completed. write device erasure and programming are accomplished via the command register. the contents of the register serve as input to the internal state machine. the state machine outputs dictate the function of the device. the command register itself does not occupy an addressable memory location. the register is a latch used to store the command, along with address and data information needed to execute the command. the command register is written by bringing we to a logic low level (v i l ), while ce is low and oe is at v i h . addresses are latched on the falling edge of we or ce , whichever happens later. data is latched on the rising edge of the we or ce whichever occurs first. standard microprocessor write timings are used. refer to ac program characteristics and waveforms, figures 3, 8and13. command definitions device operations are selected by writing specific address and data sequences into the command register. table 3 defines these register command sequences. read/reset command the read or reset operation is initiated by writing the read/reset command sequence into the command register. microprocessor read cycles retrieve array data from the memory. the device remains enabled for reads until the command register contents are altered. the device will automatically power-up in the read/reset state. in this case, a command sequence is not required to read data. standard microprocessor read cycles will retrieve array data. the device will automatically power-up in the read/reset state. in this case, a command sequence is not required to read data. standard microprocessor read cycles will retrieve array data. this table 1 ? bus operations operation ce oe we a0 a1 a9 i/o read l l h a 0 a 1 a 9 dout standby h x x x x x high z output disable l h h x x x high z write l h l a 0 a 1 a 9 d i n enable sector protect l v i d l x x v i d x verify sector protect l l h l h v i d code table 2 ? sector addresses table a16 a15 a14 address range sa0 0 0 0 00000h ? 03fffh sa1 0 0 1 04000h ? 07fffh sa2 0 1 0 08000h ? 0bfffh sa3 0 1 1 0c000h ? 0ffffh sa4 1 0 0 10000h ? 13fffh sa5 1 0 1 14000h ? 17fffh sa6 1 1 0 18000h ? 1bfffh sa7 1 1 1 1c000h ? 1ffffh
aeroflex circuit technology scd1667 rev a 4/28/97 plainview ny (516) 694-6700 6 default value ensures that no spurious alteration of the memory content occurs during the power transition. refer to the ac read characteristics and figure 7 for the specific timing parameters. byte programing the device is programmed on a byte-byte basis. programming is a four bus cycle operation. there are two "unlock" write cycles. these are followed by the program set-up command and data write cycles. addresses are latched on the falling edge of ce or we , whichever occurs later, while the data is latched on the rising edge of ce or we whichever occurs first. the rising edge of ce or we (whichever happens first) begins programming using the embedded program algorithm. upon executing the program algorithm command sequence the system is not required to provide further controls or timings. the device will automatically provide adequate internally generated program pulses and verify the programmed cell. the automatic programming operation is completed when the data on d 7 ( also used as data polling) is equivalent to data written to this bit at which time the device returns to the read mode and addresses are no longer latched. therefore, the device requires that a valid address be supplied by the system at this particular instance of time for data polling operations. data polling must be performed at the memory location which is being programmed. any commands written to the chip during the embedded program algorithm will be ignored. programming is allowed in any sequence and across sector boundaries. beware that a data "0" cannot be programmed back to a ?1". attempting to do so may cause the device to exceed programming time limits (d5 = 1) or result in an apparent success, according to the data polling algorithm, but a read from reset/read mode will show that the data is still ?0". only erase operations can convert ?0"s to ?1"s. figure 3 illustrates the programming algorithm using typical command strings and bus operations. chip erase chip erase is a six bus cycle operation. there are two 'unlock' write cycles. these are followed by writing the ?set-up? command. two more ?unlock? write cycles are then followed by the chip erase command. chip erase does not require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequence (figure 4) the device will automatically program and verify the entire memory for an all zero data pattem prior to electrical erase. the erase is performed concurrently on all sectors at the same time . the system is not required to provide any controls or timings during these operations. note: post erase data state is all "1"s. the automatic erase begins on the rising edge of the last we pulse in the command sequence and terminates when the data on d7 is "1" (see write operation status section - table 3) at which time the device retums to read mode. see figures 4 and9. sector erase sector erase is a six bus cycle operation. there are two "unlock" write cycles. these are followed by writing the "setup" command. two more "unlock" write cycles are then followed by the sector erase command. the sector address (any address location within the desired sector) is latched on the falling edge of we , while the command (30h) is latched on the rising edge of we . after a time-out of 80s from the rising edge of the last sector erase command, the sector erase operation will begin. multiple sectors may be erased concurrently by writing the six bus cycle operations as described above. this sequence is followed with writes of the sector erase command to addresses in other sectors desired to be concurrently erased. the time between writes must be less than 80s otherwise that command will not be accepted and erasure will start. it is recommended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can be re-enabled after the last sector erase command is written. a time-out of 80s from the rising edge of the last we will initiate the execution of the sector erase command(s). if another falling edge of the we occurs table 3 ? commands definitions command sequence bus write cycle req?d first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr data addr data addr data addr data addr data addr data read/reset 4 5555h aah 2aaah 55h 5555h f0h ra rd byte program 6 5555h aah 2aaah 55h 5555h a0h pa pd chip erase 6 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h sector erase 6 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa 30h notes : 1. address bit a15 = x = don't care. write sequences may be initiated with a15 in either state. 2. address bit a16 = x = don't care for all address commands except for program address (pa) and sector address (sa). 3. ra = address of the memory location to be read pa = address of the memory location to be programmed. addresses are latched on the falling edge of the we pulse. sa = address of the sector to be erased. the combination of a16, a15, a14 will uniquely select any sector. 4. rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the rising edge of we .
aeroflex circuit technology scd1667 rev a 4/28/97 plainview ny (516) 694-6700 7 within the 80s time-out window the timer is reset. (monitor d3 to determine if the sector erase timer window is still open, see section d3, sector erase timer.) any commarid other than sector erase during this period will reset the device to read mode, ignoring the previous command string. in that case, restart the erase on those sectors and allow them to complete. loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 7). sector erase does not require the user to program the device prior to erase. the device automatically programs all memory locations in the sector(s) to be erased prior to electrical erase. when erasing a sector or sectors the remaining unselected sectors are not affected. the system is not required to provide any controls or timings during these operations. post erase data state is all "1"s. the automatic sector erase begins after the 80s time out from the rising edge of the we pulse for the last sector erase command pulse and terminates when the data on d7, data polling, is ?1" (see write operatlon status secton) at which time the device returns to read mode. data polling must be performed at an address within any of the sectors being erased. figure 4 illustrates the embedded erase algorithm. data protection the act-f128k32 is designed to offer protection against accidental erasure or programming caused by spurious system level singles that may exist during power transitions. during power up the device automatically resets the internal state machine in the read mode. also, with its control register architecture, alteration of the memory content only occurs after successful completion of specific multi-bus cycle command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting from vcc power-up and power-down transitions or system noise. low v cc write inhibit to avoid initiation of a write cycle during vcc power-up and power-down, a write cycle is locked out for v c c less than 3.2v (typically 3.7v). if v c c aeroflex circuit technology scd1667 rev a 4/28/97 plainview ny (516) 694-6700 8 d 5 exceeded timing limits d 5 will indicate if the program or erase time has exceeded the specified limits. under these conditions d 5 will produce a "1". the program or erase cycle was not successfully completed. data polling is the only operation function of the device under this condition. the ce circuit will partially power down the device under these conditions by approximately 8 ma per chip. the oe and we pins will control the output disable functions as shown in table 1. to reset the device, write the reset command sequence to the device. this allows the system to continue to use the other active sectors in the device. d4 - hardware sequence flag if the device has exceeded the specified erase or program time and d5 is "1", then d4 will indicate which step in the algorithm the device exceeded the limits. a "0" in d4 indicates in programming, a "1" indicates an erase. (see table 4) d 3 sector erase timer after the completion of the initial sector erase command sequence the sector erase time-out will begin. d 3 will remain low until the time-out is complete. data polling and toggle bit are valid after the initial sector erase command sequence. if data polling or the toggle bit indicates the device has been written with a valid erase command, d 3 may be used to determine if the sector erase timer window is still open. if d 3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by data polling or toggle bit. if d 3 is low ("0"), the device will accept additional sector erase commands. to ensure the command has been accepted, the software should check the status of d 3 prior to and following each subsequent sector erase command. if d 3 were high on the second status check, the command may not have been accepted. sector protection algorithims sector protection the act-f128k32 features hardware sector protection which will disable both program and erase operations to an individual sector or any group of sectors. to activate this mode, the programming equipment must force v i d on control pin oe and address pin a 9 . the sector addresses should be set using higher address lines a 16 , a 15 , and a 14 . the protection mechanism begins on the falling edge of the we pulse and is terminated with the rising edge of the same. it is also possible to verify if a sector is protected during the sector protection operation. this is done by setting ce = oe = v i l and we = v i h (a 9 remains high at v i d ). reading the device at address location xxx2h, where the higher order addresses (a16, a15 and a14) define a particular sector, will produce 01h at data outputs d0 - d7, for a protected sector. sector unprotect the act-f128k32 also features a sector unprotect mode, so that a protected sector may be unprotected to incorporate any changes in the code. all sectors should be protected prior to unprotecting any sector. to activate this mode, the programming equipment must force v i d on control pins oe , ce , and address pin a9. the address pins a 6 , a 7 , and a 12 should be set to v i h , and a 6 = v i l . the unprotection mechanism begins on the falling edge of the we pulse and is terminated with the rising edge of the same. it is also possible to determine if a sector is unprotected in the system by writing the autoselect command. performing a read operation at address location xxx2h, where the higher order addresses (a 16 , a 15 , and a 14 ) define a particular sector address, will produce 00h at data outputs (d 0 -d 7 ) for an unprotected sector. table 4 ? hardware sequence flags in progress status d 7 d 6 d 5 d 4 d 3 d 2 ? d 0 auto-programming d 7 toggle 0 0 0 reserved for future use programming in auto erase 0 toggle 0 0 1 erase in auto erase 0 toggle 0 1 1 exceeding time limits auto-programming d 7 toggle 1 0 0 reserved for future use programming in auto erase t0 toggle 1 0 1 erase in auto erase 0 toggle 1 1 1
aeroflex circuit technology scd1667 rev a 4/28/97 plainview ny (516) 694-6700 9 ce we oe data d 0 -d 7 t o e h t o e s d6=toggle d6 valid t o e d6=toggle stop toggle d 0 -d 7 figure 1 ac waveforms for toggle bit during embedded algorithm operations i o l parameter typical units input pulse level 0 ? 3.0 v input rise and fall 5 ns input and output timing reference 1.5 v output lead capacitance 50 pf notes: 1) v z is programmable from -2v to +7v. 2) i o l and i o h programmable from 0 to 16 ma. 3) tester impedance z o =75 w. 4) v z is typically the midpoint of v o h and v o l . 5) i o l and i o h are adjusted to simulate a typical resistance load circuit. 6) ate tester includes jig capacitance. i o h to device under test v z ~ 1.5 v (bipolar supply) current source current source c l = 50 pf figure 2 ac test circuit
aeroflex circuit technology scd1667 rev a 4/28/97 plainview ny (516) 694-6700 10 bus operations command sequence comments standby write program valid address/data sequence read data polling to verify programming standby compare data output to data expected figure 3 programming algorithm start write program command sequence data poll device last address increment address (see below) no yes programming complete 5555h/aah 2aaah/55h 5555h/a0h programming address/program data program command sequence (address/command): ?
aeroflex circuit technology scd1667 rev a 4/28/97 plainview ny (516) 694-6700 11 bus operations command sequence comments standby write erase read data polling to verify erasure standby compare output to ffh figure 4 erase algorithm start erasure completed write erase command sequence (see below) data poll or toggle bit successfully completed chip erase command sequence (address/command) individual sector/multiple sector (address/command) erase command sequence 5555h/aah 2aaah/55h 5555h/80h 5555h/aah 2aaah/55h 5555h/10h 5555h/80h 5555h/aah 2aaah/55h 5555h/aah 2aaah/55h sector address/30h sector address/30h sector address/30h additional sector erase commands are optional note 1. to ensure the command has been accepted, the system software should check the status of d3 prior to and following each subsequent sector erase command. if d3 were high on the second status check, the command may not have been accepted.
aeroflex circuit technology scd1667 rev a 4/28/97 plainview ny (516) 694-6700 12 start read byte d 0 -d 7 address = va d 6 = toggle d 5 = 1 read byte d 0 -d 7 address = va fail pass yes no no yes no ? d 6 = toggle? (note 1) yes va = byte address for programming = any of the sector addresses within the sector being erased during sector erase operation = xxxxh during chip erase figure 5 toggle bit algorithm start read byte d 0 -d 7 address = va d 7 = data d 5 = 1 read byte d 0 -d 7 address = va fail pass yes no no yes no d 7 = toggle? (note 1) yes figure 6 data polling algorithm note 1. d 6 is rechecked even if d 5 = "1" because d 6 may stop toggling at the same time as d 5 changes to "1". note 1. d 7 is rechecked even if d 5 = "1" because d 7 may change simultaneously with d 5. va = byte address for programming = any of the sector addresses within the sector being erased during sector erase operation = xxxxh during chip erase ? ? ?
aeroflex circuit technology scd1667 rev a 4/28/97 plainview ny (516) 694-6700 13 ac waveforms for read operations figure 7 t o h t c e t o e t a c c t r c t d f output valid high z high z outputs oe we ce addresses addresses stable we oe ce data addresses 5.0v 5555h pa data polling pa d7 d o u t pd aoh t w h w h 1 t o e t r c t c e t d f t o h t a h t a s t d h t w p h t w p t d s t c e t w c write/erase/program figure 8 operation, we controlled notes: 1. pa is the address of the memory location to be programmed. 2. pd is the data to be programmed at byte address. 3. d7 is the 0utput of the complement of the data written to the deviced. 4. dout is the output of the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence. t g h w l
aeroflex circuit technology scd1667 rev a 4/28/97 plainview ny (516) 694-6700 14 ac waveforms chip/sector figure 9 erase operations data addresses v c c 5555h data polling t a h ce t a s we 5555h 5555h sa 2aaah 2aaah t g h w l t w p t w p h t d s t d h t c e t v c e 55h aah 80h 55h 10h/30h aah oe notes: 1. sa is the sector address for sector erase. ac waveforms for data polling figure 10 during embedded algorithm operations t o e t c h t w h w h 1 or 2 t o e t o h t d f t c e t o e h * * d7=valid data (the device has completed the embedded operation). d0?d6=invalid d7 d7= valid data d0?d6 valid data high z ce d7 oe we d0-d6
aeroflex circuit technology scd1667 rev a 4/28/97 plainview ny (516) 694-6700 15 start data = 01h set up sector address (a 16 , a 15 , a 14 ) figure 11 sector protection algorithm plscnt = 1 a 9 = v i d , ce = v i l oe = v i d activate we pulse time out 100s power down oe a9 should remain v i d ce = oe = v i h we = v i h address = sa, a 0 = 0, a 1 = 1, a 6 = 0 read from sector plscnt = 25 increment plscnt protect sector? another device failure remove v i d from a 9 write reset command sector protection complete yes yes no no no ? yes ?
aeroflex circuit technology scd1667 rev a 4/28/97 plainview ny (516) 694-6700 16 sector unprotect algorithm figure 12 start data = 00h set up sector address unprotected mode activate we pulse time out 10ms set a 1 = 1, a 0 = 0 setup sector address sa0 plscnt = 1000 address = sa7 sector device failure write reset command sector unprotect completed yes yes no set v c c = 5.0 v (a 12 = a 7 = v i h , a 6 = v i l ) oe = ce = a 9 = v i d set set oe = ce = v i l remove v i d from a9 ? read data from device increment plscnt increment sector address no ? yes no ? notes: sa0 = sector address for initial sector sa7 = sector address for last sector please refer to table 2 plscnt = 1 protect all sectors set v c c = 5.0 v set v c c = 4.25 v set v c c = 5.0 v write autoselect command sequence write reset command
aeroflex circuit technology scd1667 rev a 4/28/97 plainview ny (516) 694-6700 17 write/erase/program operation, ce controlled figure 13 ce oe we data addresses 5.0v 5555h pa data polling pa d7 d o u t pd aoh t w h w h 1 t a h t a s t d h t c p h t c p t d s t w s t w c t g h e l notes: 1. pa is the address of the memory location to be programmed. 2. pd is the data to be programmed at byte address. 3. d7 is the 0utput of the complement of the data written to the device. 4. d o u t is the output of the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence.
aeroflex circuit technology scd1667 rev a 4/28/97 plainview ny (516) 694-6700 18 pin numbers & functions 66 pins ? pga pin# function pin# function pin# function pin# function 1 i/o 8 18 a 15 35 i/o 25 52 we 3 2 i/o 9 19 vcc 36 i/o 26 53 ce 3 3 i/o 10 20 ce 1 37 a 7 54 gnd 4 a 14 21 nc 38 a 12 55 i/o 19 5 a 16 22 i/o 3 39 nc 56 i/o 31 6 a 11 23 i/o 15 40 a 13 57 i/o 30 7 a 0 24 i/o 14 41 a 8 58 i/o 29 8 nc 25 i/o 13 42 i/o 16 59 i/o 28 9 i/o 0 26 i/o 12 43 i/o 17 60 a 1 10 i/o 1 27 oe 44 i/o 18 61 a 2 11 i/o 2 28 nc 45 v c c 62 a 3 12 we 2 29 we 1 46 ce 4 63 i/o 23 13 ce 2 30 i/o 7 47 we 4 64 i/o 22 14 gnd 31 i/o 6 48 i/o 27 65 i/o 21 15 i/o 11 32 i/o 5 49 a 4 66 i/o 20 16 a 10 33 i/o 4 50 a 5 17 a 9 34 i/o 24 51 a 6 all dimensions in inches 1.085 sq 1.000 .600 1.000 .100 .020 .016 .100 .180 typ 1.030 1.040 .160 pin 56 pin 66 pin 11 pin 1 bottom view (p7 & p3) max max "p3" ? 1.08" sq pga type (without shoulder) package "p7" ? 1.08" sq pga type (with shoulder) package 1.030 1.040 .020 .016 .100 .025 .185 max side view (p7) side view (p3) .050 .180 typ .035
aeroflex circuit technology scd1667 rev a 4/28/97 plainview ny (516) 694-6700 19 pin numbers & functions 68 pins ? cqfp package pin# function pin# function pin# function pin# function 1 gnd 18 gnd 35 oe 52 gnd 2 ce 3 19 i/o 8 36 ce 2 53 i/o 23 3 a 5 20 i/o 9 37 nc 54 i/o 22 4 a 4 21 i/o 10 38 we 2 55 i/o 21 5 a 3 22 i/o 11 39 we 3 56 i/o 20 6 a 2 23 i/o 12 40 we 4 57 i/o 19 7 a 1 24 i/o 13 41 nc 58 i/o 18 8 a 0 25 i/o 14 42 nc 59 i/o 17 9 nc 26 i/o 15 43 nc 60 i/o 16 10 i/o 0 27 v c c 44 i/o 31 61 v c c 11 i/o 1 28 a 11 45 i/o 30 62 a 10 12 i/o 2 29 a 12 46 i/o 29 63 a 9 13 i/o 3 30 a 13 47 i/o 28 64 a 8 14 i/o 4 31 a 14 48 i/o 27 65 a 7 15 i/o 5 32 a 15 49 i/o 26 66 a6 16 i/o 6 33 a 16 50 i/o 25 67 we 1 17 i/o 7 34 ce 1 51 i/o 24 68 ce 4 "f5" ? single-cavity cqfp top view all dimensions in inches 0.015 0.990 sq .010 0.880 sq .010 0.800 ref 0.050 see detail ?a? typ .010 pin 60 pin 44 pin 43 pin 27 pin 26 pin 10 pin 9 pin 61 side view 0.946 .010 0.160 max detail ?a? 0.010 3-3 0.040 .010 r 0.010 .005 ref
aeroflex circuit technology scd1667 rev a 4/28/97 plainview ny (516) 694-6700 20 ordering information model number desc drawing number speed package act?f128k32n?060p3q 5962-9471605hzx * 60 ns pga act?f128k32n?070p3q 5962-9471604hzc 70 ns pga act?f128k32n?090p3q 5962-9471603hzc 90 ns pga act?f128k32n?120p3q 5962?9471602hzc 120 ns pga act?f128k32n?150p3q 5962?9471601hzc 150 ns pga act?f128k32n?060p7q 5962-9471605h8x * 60 ns pga act?f128k32n?070p7q 5962-9471604h8c 70 ns pga act?f128k32n?090p7q 5962-9471603h8c 90 ns pga act?f128k32n?120p7q 5962?9471602h8c 120 ns pga act?f128k32n?150p7q 5962?9471601h8c 150 ns pga act?f128k32n?060f5q 5962-9471605hnx * 60 ns cqfp act?f128k32n?070f5q 5962-9471604hnc 70 ns cqfp act?f128k32n?090f5q 5962-9471603hnc 90 ns cqfp act?f128k32n?120f5q 5962?9471602hnc 120 ns cqfp act?f128k32n?150f5q 5962?9471601hnc 150 ns cqfp * pending circuit technology act? f 128k 32 n? 060 f5 q aeroflex circuit technology memory type f = flash eeprom memory depth options memory width, bits n = none memory speed, ns package type & size c = commercial temp, 0c to +70c i = industrial temp, -40c to +85c t = military temp, -55c to +125c m = military temp, -55c to +125c, screened * q = mil-std-883 compliant/smd if applicable screening part number breakdown surface mount packages thru-hole packages f5 = .88"sq 68 lead single-cavity cqfp p3 = 1.075"sq pga 66 pins w/o shoulder p7 = 1.075"sq pga 66 pins with shoulder * screened to the individual test methods of mil-std-883 aeroflex circuit technology 35 south service road plainview new york 11830 telephone: (516) 694-6700 fax: (516) 694-6715 toll free inquiries: 1-(800) 843-1553 specification subject to change without notice

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